The present invention relates, in general, to semiconductor devices and, more particularly, to vertical semiconductor devices.
Vertical semiconductor devices such as, for example, vertically diffused field effect transistors are commonly used as high power devices in electronic circuits. A conventional vertically diffused field effect transistor usually has its gate electrode and source electrode on the front side of a semiconductor die on which the transistor is fabricated. The drain electrode of the transistor is typically on the back side of the die. Inter-chip or inter-die wiring is conventionally used for coupling the drain electrode of the transistor to other elements in the circuit. The inter-chip wiring requires back side metal plating and wire bonding, which are complicated and expensive. As the complexity of the circuit increases, the number and complexity of the interconnections between different dies in the circuit also increase. Consequently, the inter-chip wiring process becomes increasingly expensive and increasingly difficult to perform.
Accordingly, it would be advantageous to have a vertical semiconductor device on a chip and a method for fabricating the device, so that the device can be coupled to an off-chip circuit element without wire-bonding to the back side of the chip. It is desirable for the device to be compatible with a simple and cost efficient packaging process. It is also desirable for the device and the interconnection between the device and other circuit elements in a circuit to be simple, reliable, and cost efficient. It would be of further advantage for the method for fabricating the device to be simple and compatible with existing semiconductor device fabricating processes.